1. Field of the Invention
This invention generally relates to communication protocol and, more particularly, to a system and method for maintaining virtual lane forward error correction (FEC) in a multilane network.
2. Description of the Related Art
Conventionally, both optical and electrical communications have been carried a single communication channel. The Multi-lane Distribution (MLD) protocol, as specified by both the IEEE and ITU, is meant to allow a stream of serial traffic to be transmitted over distinct parallel channels. MLD protocol takes a serial stream and breaks it in smaller blocks. These blocks are then assigned a Lane or virtual lane number. Each virtual lane has the characteristic that a periodic pattern is uniquely present on each lane. The pattern is periodic and the time shift between lane markers is deterministic. These characteristics make it possible to reconstruct the original serial sequence at a receiver after these signals have traveled over different media, such as fiber, copper, or lambdas.
The number of virtual lanes into which a serial stream is broken depends on the set of parallel media over which the signals are transported. If a signal can be transported over 10, 5, 4, 2 or 1 media, 20 VL are required to always accommodate the same number of virtual lanes on each medium. For example, in the case where there are 4 media (physically separated channels) and 20 VLs, then 5 VLs travel over the same media at any given time, single bit interleaved or x-bit interleaved.
One of the properties of the MLD interface is that once a VL is assigned to a media, it will travel over the same media for the reminder of the communication. Therefore, once the receiver is able to synchronize over the multiple virtual lanes being transported on each channel, the receiver is able to reconstruct the original serial stream.
However, one problem does arise when adapting the MLD protocol to Optical Transport Network (OTN) communications over multiple media. FEC in communication systems is intended to correct errors occurring in a particular channel. Conventionally, the payload portion of the signal and the parity portion of the signal (FEC) have shared the same medium in OTN networks. Since the FEC and payload share the same medium, the performance monitoring parameters, such as corrected 0s and corrected 1s from the FEC decoder, have been used to send feedback to the receiver and equalizer to correct the thresholds of the incoming signal.
However, in parallel communication systems there are multiple receivers and, therefore, each receiver can use different parameters to interpret the received signal. Some example of parallel communication systems include: Wavelength Division Multiplexing (WDM), Polarization Multiplexing, x-QAM, and x-PSK modulation. The OTN FEC interleaving schemes currently specified in G.709 and in the appendix of G.975.1, when combined with MLD, break the linkage between a channel and the FEC information needed to correct that channel. Since FEC and payload are no longer associated with the same transmitter and receiver, it is no longer possible to correlate the decoder FEC performance monitoring parameters with a particular transmission channel.
The lack of correlation between error rate and pre-FEC decoder error rate renders it impossible to tweak the equalization parameters, the receiver thresholds, and the CDC (chromatic dispersion compensators) parameters, as is conventionally done for single-channel systems.
FIG. 1 a diagram depicting an OTU3 (43 gigabit per second (43 Gbs)) MLD interface using 4 Virtual Lanes (VLs) (prior art).
FIG. 2 a diagram depicting an OTU4 (100 gigabit Ethernet—100 GbE) MLD interface using 20 VLs (prior art). The ITU calls for a VL rotation on a per frame basis, as shown. The basic concept for performing the striping in FIGS. 1 and 2 is as follows:                Stripe in 16 byte blocks starting with bytes 1 to 16 of the frame;        Rotate the order of the mapping from the OTN frame to the VLs at each OTN frame boundary, so that the existing frame alignment signal appears on each lane successively;        For OTU3, the MFAS from every fourth frame appears in each lane so this can be used as lane ID;        Overwrite the last A-2 byte for STM-256 or the last OA2 byte for OTU4 with lane ID;        If a new frame counter field is created for OTU4 which is always present and which repeats over a multiple of 20 frames, use this as the lane ID.        
The above-described scheme results in a set of parallel signals, each of which will have a marker every 4080*4 bytes. Each signal marker has a common portion FAS that can be used for alignment purpose and a unique portion that can be used to identify each virtual lane. Additional details of this striping scheme can be found in U.S. Pat. No. 7,362,779, issued Apr. 22, 2008, entitled TRANSMISSION OF DATA FRAMES AS A PLURALITY OF SUBFRAMES OVER A PLURALITY OF CHANNELS, invented by Vladimir Zabezhinsky, which is incorporated herein by reference.
The conventional OTN row is defined as a structure with 3824 payload bytes and 256 FEC parity bytes, where 1 frame is equal to 4 rows. This creates a ratio of 239 (payload) to 16 (FEC). In the case where each VL block is 16 bytes, there are 239 blocks of payload and 16 blocks of FEC per row or 239*4 payload and 64 FEC. When 20 VLs are used, the number of VL blocks resident in the FEC area is not equal for all virtual lanes. Only over the combined sum of 20 OTN frames is it possible to find the same ratio of payload to FEC (239/16) in the VL blocks as in the single channel implementation.
One possible solution is to separately frame each VL, creating the same structure as a conventional OTN frame. However, the solution introduces significant latency—20 times the latency of the conventional OTN decoder. Conventionally, the OTN decoder delay for G.709 FEC is 1 OTN row, which would become 20 OTN rows using the above-proposed solution. Added latency not only increases overall signal delay, but also increases the memory requirements by 20-fold. Further, statistic would have to maintained on a per virtual lane basis, multiplying the complexity of the encoders and decoders.
One might try to solve the problem of latency by reducing the current interleaving specified in the FEC in order to shorten the latency and reduce the required memory. This creates a problem when there is a high level of parallelism (e.g., 10 lanes), as the signal becomes more susceptible to burst error when the number of interleaved codewords is reduced.
It would be advantageous if FEC corrections and virtual lanes could be properly correlated in an MLD OTN network, with a minimum of added latency and buffering requirements.